Texas InstrumentsVerified
Design Verification Engineer
- Salary
- ₹10–17 LPA
- Location
- Bangalore, India
- Level
- Entry
- Experience
- Fresher · 1+ years
Verified direct application link, checked by Astra
About the company & role
Bachelor's or Master's in Electrical or Electronics Engineering; proven experience in mixed-signal testbenches in SV/UVM; strong debug skills; familiarity with analog controllers; 1-3 years preferred experience; proficiency in Cadence tools, SystemVerilog, UVM, Verilog-AMS, and scripting.