MetaVerified
ASIC Engineer Intern, Physical Design
- Stipend
- ₹35,000–₹60,000/month
- Region
- 🌐 Global
- Work mode
- Onsite
- Category
- Engineering
VerilogSystemVerilogTCLPython
Verified direct application link, checked by Astra
About the company & role
Currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering or related field; knowledge of computer architecture, logic design, device physics, Verilog, SystemVerilog; must obtain work authorization; intent to return to degree program after internship.